Double-click on Simulate Behavioral Model and ModelSim will open, compile your full adder module and run the simulation code. Expanding the ModelSim Simulator item reveals the possible simulation options. Once you have written and saved your test fixture, click on it in the Sources in Project window, then click on the Process View tab below. Write the rest of the simulation code yourself if you need help, you can view a completed test fixture here.

Since the full adder only has three one-bit inputs, there are only eight possible input combinations, and your test fixture should simulate them all. Values can also be represented in decimal and hexadecimal for example, 8'd27 represents 00011011 and 4'hA represents 1010.Ī good test fixture will test all or most of the possible inputs to the module, and especially any corner/boundary cases. For example, the following code tests when each of the inputs are high separately, changing the inputs every 25 ns:įor the value 1'b0, the 1 represents the number of bits, the b stands for binary and the 0 represents the 1-bit binary value. Between assignments, delays are inserted using #n, where n is the number of nanoseconds of delay. Simulate your module by assigning different values to the inputs and observing the outputs. The values are initialized, and your code goes under the 'Add stimulus here' line. The full_adder module is instantiated and the simulation begins after the 'initial begin' line. The inputs to the module are registers ('reg') because they are assigned in a procedural block (the section between 'begin' and 'end'). ISE creates a skeleton test fixture for you. Click Next, and you'll be prompted to associate the file with a module choose full_adder, click Next, then click Finish.

Select Verilog Test Fixture and give your file a name such as 'test_full_adder'. Right-click on full_adder.v in the Sources in Project window and choose New Source. Run the Check Syntax process (under Synthesize) to make sure your code is entered correctly, and save your design. You can use your own code, or copy the solution below: This tutorial will use a full adder that is the same as the one you created in Lab 0. If you accidentally select ISE Simulator as the simulator for your project, or if you open a previous project that had the ISE Simulator selected, you can change the simulator by right-clicking on xc2vp30-7ff896 in the Sources in Project window and selecting Properties.

Xilinx modelsim